View 8XC51GB_8950982.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 272337-002 8XC51GB chmos single-chip 8-bit microcontroller commercial/express 87c51gbe8 kbytes otp/8 kbytes internal program memory 83c51gbe8 kbytes factory programmable rom 80c51gbecpu with ram and i/o 8XC51GBe3.5 mhz to 12 mhz g 20% v cc 8XC51GB-1e3.5 mhz to 16 mhz g 20% v cc y 8 kbytes on-chip rom/otp rom y 256 bytes of on-chip data ram y two programmable counter arrays with: e 2 x 5 high speed input/output channels compare/capture e pulse width modulators e watchdog timer capabilities y three 16-bit timer/counters with e four programmable modes: e capture, baud rate generation (timer 2) y dedicated watchdog timer y 8-bit, 8-channel a/d with: e eight 8-bit result registers e four programmable modes y programmable serial channel with: e framing error detection e automatic address recognition y serial expansion port y programmable clock out y extended temperature range: ( b 40 cto a 85 c) y 48 programmable i/o lines with 40 schmitt trigger inputs y 15 interrupt sources with: e 7 external, 8 internal sources e 4 programmable priority levels y pre-determined port states on reset y high performance chmos process y ttl and chmos compatible logic levels y power saving modes y 64k external data memory space y 64k external program memory space y three level program lock system y once (on-circuit emulation) mode y quick pulse programming algorithm y mcs 51 microcontroller fully compatible instruction set y boolean processor y oscillator fail detect y available in 68-pin plcc memory organization program memory: up to 8 kbytes of the program memory can reside in the on-chip rom. also, the device can address up to 64k of program memory external to the chip. data memory: this microcontroller has a 25 6 x 8 on-chip ram. in addition it can address up to 64 kbytes of external data memory. the intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on intel's chmos iii-e technology. the 8XC51GB is an enhanced version of the 8xc51fa and uses the same powerful instruction set and architecture as existing mcs 51 microcontroller products. added features make it an even more powerful microcontroller for applications that require on-chip a/d, pulse width modulation, high speed i/o, up/down counting capabilities and memory protection features. it also has a more versatile serial channel that facilitates multi-processor communications.
8XC51GB 272337 1 figure 1. 8XC51GB block diagram process information this device is manufactured on p629.0, a chmos iii-e process. additional process and reliability infor- mation is available in intel's components quality and reliability handbook, order no. 210997. packages part prefix package type 8XC51GB n 68-pin plcc 2
8XC51GB parallel i/o ports the 8XC51GB contains six 8-bit parallel i/o ports. all six ports are bidirectional and consist of a latch, an output driver, and an input buffer. many of the port pins have multiplexed i/o and control functions. port pins as outputs port 0 has open drain outputs when it is not serving as the external data bus. the internal pullup is active only when the pin is outputting a logic 1 during exter- nal memory access. an external pullup resistor is required on port 0 when it is serving as an output port. ports 1, 2, 3, 4, and 5 have quasi-bidirectional out- puts. a strong pullup provides a fast rise time when the pin is set to a logic 1. this pullup turns on for two oscillator periods to drive the pin high and then turns off. the pin is held high by a weak pullup. writing the p0, p1, p2, p3, p4 or p5 special function register sets the corresponding port pins. all six port registers are bit addressable. port pins as inputs the pins of all six ports are configured as inputs by writing a logic 1 to them. since port 0 is an open drain port, it provides a very high input impedance. since pins of port 1, 2, 3, 4 and 5 have weak pullups (which are always on), they source a small current when driven low externally. all ports except port 0 have schmitt trigger inputs. port states during reset ports 0 and 3 reset asynchronously to a one and ports 1, 2, 4, and 5 reset to a zero asynchronously. pin descriptions the 8XC51GB will be packaged in the 68-lead plcc package. its pin assignment is shown in figure 2. v cc : supply voltage. v ss : circuit ground. diagram is for pin reference only. package size is not to scale. 272337 2 * otp only figure 2. pin connections 3
8XC51GB alternate port functions ports 0, 1, 2, 3, 4 and 5 have alternate functions as well as their i/o function as described below. port pin alternate function p0.0/ado p0.7/ad7 multiplexed address/data for external memory p1.0/t2 timer 2 external clock input/clock-out p1.1/t2ex timer 2 reload/capture/direction control p1.2/eci pca external clock input p1.3/cexo p1.7/cex4 pca capture input, compare/pwm output p2.0/a8 p2.7/a15 high byte of address for external memory p3.0/rxd serial port input p3.1/txd serial port output p3.2/int0 external interrupt 0 p3.3/int1 external interrupt 1 p3.4/t0 timer 0 external clock input p3.5/t1 timer 1 external clock input p3.6/wr write strobe for external memory p3.7/rd read strobe for external memory p4.0/sepclk clock source for serial expansion port p4.1/sepdat data i/o for the serial expansion port p4.2/eci1 pca1 external clock input p4.3/c1ex0 p4.7/c1ex4 pca1 capture input, compare/pwm output p5.2/int2 p5.6/int6 external interrupt int2 int6 rst : reset input. a low on this pin for two machine cycles while the oscillator is running resets the de- vice. the port pins will be driven to their reset condi- tion when a voltage below v il max voltage is ap- plied, whether the oscillator is running or not. an internal pullup resistor permits a power-on reset with only a capacitor connected to v ss . ale/prog : address latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin (ale/prog ) is also the program pulse input during programming of the 87c51gb. in normal operation ale is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, how- ever, that one ale pulse is skipped during each ac- cess to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with this bit set, the pin is weakly pulled high. however, the ale disable fea- ture will be suspended during a movx or movc in- struction, idle mode, power down mode and ice mode. the ale disable feature will be terminated by reset. when the ale disable feature is suspended or terminated, the ale pin will no longer be pulled up weakly. setting the ale-disable bit has no affect if the microcontroller is in external execution mode. throughout the remainder of this data sheet, ale will refer to the signal coming out of the ale/prog pin, and the pin will be referred to as the ale/prog pin. psen : program store enable is the read strobe to external program memory. when the 8XC51GB is executing code from external program memory, psen is activated twice each ma- chine cycle, except that two psen activations are skipped during each access to external data memo- ry. ea /v pp : external access enable. ea must be strapped to v ss in order to enable the device to fetch code from external program memory locations 0000h to 1fffh. note, however, that if either of the program lock bits are programmed, ea will be inter- nally latched on reset. ea should be strapped to v cc for internal program executions. 4
8XC51GB this pin also receives the 12.75v programming sup- ply voltage (v pp ) during programming (otp only). xtal1: input to the inverting oscillator amplifier. xtal2: output from the inverting oscillator amplifi- er. a/d converter the 8XC51GB a/d converter has a resolution of 8 bits and an accuracy of g 1 lsb ( g 2 lsb for chan- nels 0 and 1). the conversion time for a single chan- nel is 20 m s at a clock frequency of 16 mhz with the sample and hold function included. independent supply voltages are provided for the a/d. also, the a/d operates both in normal mode or in idle mode. the a/d has 8 analog input pins; ach0 (a/d chan- nel 0) . . . ach7, 1 reference input pin; compref (comparison reference), 1 control input pin; tri- gin (trigger in), and 2 power pins; avref (volt- age reference) and analog ground (analog ground). in addition, the a/d has 8 conversion re- sult registers; adres0 (a/d result for channel 0) . . . adres7, 1 comparison result register; acmp (ana- log comparison), and 1 control register; acon (a/d control). the control bit ace (a/d conversion enable) in acon controls whether the a/d is in operation or not. ace e 0 idles the a/d. ace e 1 enables a/d conversion. the control bit aim (a/d input mode) in acon controls the mode of channel selection. aim e 0 is the scan mode, and aim e 1 is the select mode. the result registers adres4 . . . adres7 al- ways contain the result of a conversion from the cor- responding channels ach4 . . . ch7. however, the result registers adres0 . . . adres3 depend on the mode selected. in the scan mode, adres0 . . . ad- res3 contain the values from ach0 . . . ach3. in the select mode, one of the four channels ach0 . . . ach3 is converted four times, and the four values are stored sequentially in locations adres0 . . . ad- res3. its channel is selected by bits acs1 and acs0 (a/d channel select 1 and 0) in acon. programmable counter arrays the programmable counter arrays (pca pca1) are each made up of a counter module and five regis- ter/comparator modules as shown below. the 16-bit output of the counter module is available to all five register/comparator modules, providing one common timing reference. each register/compara- tor module is associated with a pin of port 1 or port 4 and is capable of performing input capture, output compare and pulse width modulation functions. the pcas are exactly the same in function except for the addition of clock input sources on pca1. the pca counter and five register/comparator modules each have a status bit in the ccon/ c1con special function registers. these six status bits are set according to the selected modes of operation described below. the ccon/c1con register provides a convenient means to determine which of the six pca/pca1 interrupts has occurred. the ec bit in the ie (interrupt enable) special func- tion register is a global interrupt enable for the pca. 272337 3 figure 3. programmable counter arrays oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 4. either a quartz crystal or ceramic resonator may be used. more detailed information concerning the use of the on-chip oscillator is available in appli- cation note ap-155, ``oscillators for microcontrol- lers,'' order no. 230659. to drive the device from an external clock source, xtal should be driven, while xtal2 floats, as shown in figure 5. there are no requirements on the duty cycle of the external clock signal, since the in- put to the internal clocking circuitry is through a di- vide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. 5
8XC51GB 272337 4 c1, c2 e 30 pf g 10 pf for crystals for ceramic resonators contact resonator manufacturer. figure 4. oscillator connections 272337 5 figure 5. external clock drive configuration idle mode the user's software can invoke the idle mode. when the microcontroller is in this mode, power consump- tion is reduced. the special function registers and the onboard ram retain their values during idle, pe- ripherals continue to operate, but the processor stops executing instructions. idle mode will be exited if the chip is reset or if an enabled interrupt occurs. the pca timer/counter can optionally be left run- ning or paused during idle mode. the watchdog timer continues to count in idle mode and must be serviced to prevent a device reset while in idle. power down mode to save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their val- ues until the power down mode is terminated. on the 8XC51GB either a hardware reset or an ex- ternal interrupt can cause an exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt does not re- define the sfr's or change the on-chip ram. an external interrupt will modify the interrupt associated sfr's in the same way an interrupt will in all other modes. the interrupt must be enabled and config- ured as level sensitive. to properly terminate power down the reset or external interrupt should not be executed before v cc is restored to its normal oper- ating level. the reset or external interrupt must be held active long enough for the oscillator to restart and stabilize. the oscillator fail detect must be dis- abled prior to entering power down. design considerations # when the idle mode is terminated by a hardware reset, the device normally resumes program exe- cution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to inter- nal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by re- set, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. # as reset rises, the 8XC51GB will remain in re- set for up to 5 machine cycles (60 oscillator peri- ods) after reset reaches v ih1 . table 1. status of the external pins during idle and power down mode program ale psen port0 port1 port2 port3 memory idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data note: for more detailed information on the reduced power modes refer to current embedded microcontrollers and processors handbook volume i (order no. 270645), and application note ap-252 (embedded applications handbook, order no. 270648), ``designing with the 80c51bh.'' 6
8XC51GB once mode the once (``on-circuit emulation'') mode facilitates testing and debugging of systems using the 8XC51GB without removing it from the circuit. the once mode is invoked by: 1) pulling ale low while the device is in reset and psen is high; 2) holding ale low as reset is deactivated. while the device is in once mode, the port 0 pins float, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains ac- tive. while the 8XC51GB is in this mode, an emula- tor or test cpu can be used to drive the circuit. nor- mal operation is restored when a normal reset is ap- plied. watchdog timer (wdt) the 8XC51GB contains a dedicated watchdog tim- er (wdt) to allow recovery from a software or hard- ware upset. the wdt consists of a 14-bit counter which is cleared on reset, and subsequently incre- mented every machine cycle. while the oscillator is running, the wdt will be incrementing and cannot be disabled. the counter may be reset by writing 1eh and e1h in sequence to the wdtrst special function register. if the counter is not reset before it reaches 3fffh (16383d), the chip will be forced into a reset sequence by the wdt. this works out to 12.28 ms @ 16 mhz. wdtrst is a write only regis- ter. the wdt does not force the external reset pin low. while in idle mode the wdt continues to count. if the user does not wish to exit idle with a reset, then the processor must be periodically ``woken up'' to service the wdt. in power down mode, the wdt stops counting and holds its current value. serial expansion port (sep) the serial expansion port is a half-duplex synchro- nous serial interface with the following features: four clock frequenciese xtal/12, 24, 48, 96. four interface modese high/low/falling/rising edges. interrupt driven. oscillator fail detect (ofd) the oscillator fail detect circuitry triggers a reset if the oscillator frequency is lower than the ofd trig- ger frequency. it can be disabled by software by writ- ing e1h followed by 1eh to the ofdcon register. before going into power down mode, the ofd must be disabled or it will force the gb out of power down. the ofd has the following features. ofd trigger frequency: below 20 khz, the 8XC51GB will be held in reset. above 400 khz, the 8XC51GB will not be held is reset. functions in normal and idle modes. reactivated by reset (or external interrupt ze- ro/one pins) after software disable. 8XC51GB express the intel express products are designed to meet the needs of those applications whose operating re- quirements exceed commercial standards. with the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of 0 cto a 70 c. with the ex- tended temperature range option, operational char- acteristics are guaranteed over the range of b 40 c to a 85 c. the 87c51gb express is packaged in the 68-lead plcc package. in order to designate a part as an express part, a ``t'' is added as a prefix to the part number. tn87c51gb denotes an ex- press part in a plcc package. all ac and dc parameters in this data sheet apply to the express devices. 7
8XC51GB absolute maximum ratings * ambient temperature under bias 0 cto a 70 c storage temperature b 65 cto a 150 c voltage on ea/v pp pin to v ss 0v to a 13.0v * i ol per i/o pin 15 ma voltage on any other pin to v ss b 0.5v to a 6.5v power dissipation1.5w (based on package heat transfer limitations, not de- vice power consumption) * otp only. notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias commercial 0 a 70 c express b 40 a 85 c v cc supply voltage 4.0 6.0 v f osc oscillator frequency 8XC51GB 3.5 12 mhz 8XC51GB-1 3.5 16 mhz dc characteristics (over operating conditions) symbol parameter min typ (1) max unit test conditions v il input low voltage b 0.5 0.2 v cc b 0.1 v (except port 2 and ea ) v il1 input low voltage b 0.5 0.2 v cc b 0.3 v (port 2) v il2 input low voltage 0 0.2 v cc b 0.3 v (ea ) v ih input high voltage 0.2 v cc a 0.9 v cc a 0.5 v (except xtal1 and rst ) v ih1 input high voltage 0.7 v cc v cc a 0.5 v (xtal1, rst ) v ol output low voltage 0.3 v i ol e 100 m a (2,3) (ports 1, 2, 3, 4 and 5) 0.45 v i ol e 1.6 ma (2,3) 1.0 v i ol e 3.5 ma (2,3) v ol1 output low voltage 0.3 v i ol e 200 m a (2,3) (port 0, psen , ale) 0.45 v i ol e 3.2 ma (2,3) 1.0 v i ol e 7.0 ma (2,3) 8
8XC51GB dc characteristics (over operating conditions) (continued) symbol parameter min typ (1) max unit test conditions v oh output high voltage v cc b 0.3 v i oh eb 10 m a (4) (ports 1, 2, 3, 4 and 5, v cc b 0.7 v i oh eb 30 m a (4) ale, psen ) v cc b 1.5 v i oh eb 60 m a (4) v oh1 output high voltage v cc b 0.3 v i oh eb 200 m a (port 0 in external v cc b 0.7 v i oh eb 3.2 ma bus mode) v cc b 1.5 v i oh eb 7.0 ma i il logical 0 input current b 50 m av in e 0.45v (ports 1, 2, 3, 4, 5) i tl logical 1-to-0 transition b 650 m av in e 2.0v current (ports 1, 2, 3, 4, 5) i li input leakage current g 10 m a 0.45 k v in k v cc (port 0) rrst rst pullup resistor 50 300 k x c io pin capacitance 10 pf freq e 1 mhz t a e 25 c i pd power down current 50 m a (5) i dl idle mode current 18 ma (5) i cc operating current @ 16 mhz 50 ma (5) i ref a/d converter reference 5 ma current notes: 1. typical values are obtained using v cc e 5.0v, t a e 25 c, and are not guaranteed. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit porte port 0: 26 ma ports 1 5: 15 ma maximum total i ol for all outputs pins: 101 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4v on the low level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt trigger, or cmos-level input logic. 4. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the 0.9 v cc specification when the address lines are stabilizing. 5. see figures 6 10 for test conditions. minimum v cc for power down is 2v. 9
8XC51GB 272337 6 i cc max at other frequencies is given by: active mode i cc max e (osc freq c 3) a 4 idle mode i cc max e (osc freq c 0.5) a 4 where osc freq is in mhz, i cc is in ma. t clch e t chcl e 5ns figure 6. i cc vs frequency 272337 7 all other pins disconnected. tclch e tchcl e 5ns figure 7. i cc test condition, active mode 272337 8 all other pins disconnected. tclch e tchcl e 5ns figure 8. i cc test condition idle mode 272337 9 all other pins disconnected. figure 9. i cc test condition, power down mode v cc e 2.0v to 5.5v 272337 10 figure 10. clock signal waveform for i cc tests in active and idle modes. tclch e tchcl e 5 ns. 10
8XC51GB explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a ``t'' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for: a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example: tavll e time from address valid to ale low tllpl e time from ale low to psen low ac specifications over operating conditions, load capacitance on port 0, ale, and psen e 100 pf, load capacitance on all other outputs e 80 pf external program and data memory characteristics symbol parameter 12 mhz osc. variable osc. units min max min max 1/tclcl osc. freq. 3.5 16 mhz tlhll ale pulse width 127 2tclcl b 40 ns tavll addr valid to ale low 43 tclcl b 40 ns tllax addr hold after ale low 53 tclcl b 30 ns tlliv ale low to valid inst. in 234 4tclcl b 100 ns tllpl ale low to psen low 53 tclcl b 30 ns tplph psen pulse width 205 3tclcl b 45 ns tpliv psen low to valid instr in 145 3tclcl b 105 ns tpxix input instr. hold after psen 00 ns tpxiz input instr. float after psen 59 tclcl b 25 ns taviv addr to valid instr. in 312 5tclcl b 105 ns tplaz psen low to addr float 10 10 ns trlrh rd pulse width 400 6tclcl b 100 ns twlwh wr pulse width 400 6tclcl b 100 ns trldv rd low to valid data in 252 5tclcl b 165 ns trhdx data hold after rd 00 ns trhdz data float after rd 107 2tclcl b 60 ns tlldv ale low to valid data in 517 8tclcl b 150 ns tavdv addr to valid data in 585 9tclcl b 165 ns tllwl ale low to rd or wr low 200 300 3tclcl b 50 3tclcl a 50 ns tavwl addr valid to rd or wr low 203 4tclcl b 130 ns tqvwx data valid to wr transition 33 tclcl b 50 ns twhqx data hold after wr 33 tclcl b 50 ns tqvwh data valid to wr high 433 7 tclcl b 150 ns trlaz rd low to addr float 0 0 ns twhlh rd or wr high to ale high 43 123 tclcl b 40 tclcl a 40 ns 11
8XC51GB external program memory read cycle 272337 11 external data memory read cycle 272337 12 external data memory write cycle 272337 13 12
8XC51GB serial port timingeshift register mode test conditions: over operating conditions, load capacitance e 80 pf symbol parameter 12 mhz variable units oscillator oscillator min max min max txlxl serial port clock 1 12tclcl m s cycle time tqvxh output data setup to 700 10tclcl b 133 ns clock rising edge txhqx output data hold after 50 2tclcl b 117 ns clock rising edge txhdx input data hold after 0 0 ns clock rising edge txhdv clock rising edge to 700 10tclcl b 133 ns input data valid shift register mode timing waveforms 272337 14 external clock drive symbol parameter min max units 1/tclcl oscillator frequency 3.5 16 mhz tchcx high time 20 ns tclcx low time 20 ns tclch rise time 20 ns tchcl fall time 20 ns external clock drive waveform 272337 15 13
8XC51GB sep ac timing specifications test conditions: over operating conditions, load capacitance e 80 pf symbol parameter 12 mhz variable units oscillator oscillator min max min max txsxl sepclk cycle time 1 12 tclcl m s txsst output data setup to sepclk 435 6 tclcl b 65 ns txsoh output data hold after sepclk 445 6 tclcl b 55 ns txsih input data hold after sepclk 210 2 tclcl a 43 ns sampling edge txsdv input data valid to sepclk 947 12 tclcl b 53 ns sampling edge sep waveform (seps1 e 0; seps0 e 0; clkpol e 0; clkph e 0) 272337 16 272337 17 14
8XC51GB ac testing input, output waveforms 272337 18 ac inputs during testing are driven at v cc b 0.5v for a logic ``1'' and 0.5v for a logic ``0''. timing measurements are made at v ih for a logic ``1'' and v ol max for a logic ``0''. float waveforms 272337 19 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh t g 20 ma. a to d characteristics the absolute conversion accuracy is dependent on the accuracy of av ref . the specifications given be- low assume adherence to the operating conditions section of this data sheet. testing is done at av ref e 5.12v, and v cc e 5.0v. operating conditions v cc 4.0v to 6.0v av ref 4.5v to 5.5v v ss ,av ss 0v ach0 7 av ss to v ref t a 0 cto a 70 c ambient fosc (std version)3.5 mhz to 12 mhz fosc (-1 version) 3.5 mhz to 16 mhz a/d converter specifications t a e 0 cto a 70 c parameter min typ * max units ** notes resolution 256 256 levels 8 8 bits absolute error (ch 2 7) 0 g 1 lsb absolute error (ch 0 and 1) 0 g 2 lsb full scale error g 1 lsb zero offset error g 1 lsb non-linearity 0 g 1 lsb differential non-linearity 0 g 1 lsb channel-to-channel matching 0 g 1 lsb repeatability g 0.25 lsb 15
8XC51GB a/d converter specifications t a e 0 cto a 70 c (continued) parameter min typ * max units ** notes temperature coefficients: offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c input capacitance 3 pf off isolation b 60 db (8, 9) feedthrough b 60 db (8) v cc power supply rejection b 60 db (8) input resistance to 750 1.2k x sample-and-hold capacitor dc input leakage 0 3.0 m a notes: * these values are expected for most parts at 25 c ** an ``lsb'' as used here, has a value of approximately 20 mv. 8. dc to 100 khz 9. multiplexer break-before-make guaranteed. 10. there is no indication when a single a/d conversion is complete. please refer to the 8XC51GB hardware description on how to read a single a/d conversion. 11. t cy e 12 tclcl a/d conversion time notes per channel 26 t cy (10, 11) 8 conversions 208 t cy (11) 16
8XC51GB programming the otp the part must be running with a 4 mhz to 6 mhz oscillator. the address of a location to be pro- grammed is applied to address lines while the code byte to be programmed in that location is applied to data lines. control and program signals must be held at the levels indicated in table 2. normally ea /v pp is held at logic high until just before ale/prog is to be pulsed. the ea /v pp is raised to v pp , ale/prog is pulsed low and then ea /v pp is returned to a high (also refer to timing diagrams). note: exceeding the v pp maximum for any amount of time could damage the device permanently. the v pp source must be well regulated and free of glitches. definition of terms address lines: p1.0 p1.7, p2.0 p2.4, respec- tively for a0 a12. data lines: p0.0 p0.7 for d0 d7. control signals: rst , psen , p2.6, p2.7, p3.3, p3.6, p3.7 program signals: ale/prog ,ea /v pp 272337 20 * see table 2 for proper input on these pins. figure 11. programming the otp table 2. otp programming modes mode rst psen ale/ ea / p2.6 p2.7 p3.3 p3.6 p3.7 prog v pp program code data l l ? 12.75v l h h h h verify code data l l h h l l l h h program encryption l l ? 12.75v l h h l h array address 0 3fh program lock bit 1 l l ? 12.75v h h h h h bits bit 2 l l ? 12.75v h h h l l bit 3 l l ? 12.75v h l h h l read signature byte l h h h lllll 17
8XC51GB programming algorithm refer to table 2 and figures 11 and 12 for address, data, and control signals set up. to program the 87c51gb the following sequence must be exer- cised. 1. input the valid address on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control sig- nals. 4. raise ea /v pp from v cc to 12.75v g 0.25v. 5. pulse ale/prog 5 times for the otp array, and 25 times for the encryption table and the lock bits. repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. program verify program verify may be done after each byte that is programmed, or after a block of bytes that is pro- grammed. in either case a complete verify of the array will ensure that it has been programmed cor- rectly. the lock bits cannot be directly verified. verification of the lock bits is done by observing that their fea- tures are enabled. refer to the program lock sec- tion in this data sheet. 272337 21 figure 12. programming signal's waveforms 18
8XC51GB rom and eprom lock system the 87c51gb and the 83c51gb program lock sys- tems, when programmed, protect the on-board pro- gram against software piracy. the 83c51gb has a one-level program lock system and a 64-byte encryption table. see line 2 of table 3. if program protection is desired, the user submits the encryption table with their code, and both the lock bit and encryption array are programmed by the factory. the encryption array is not available without the lock bit. for the lock bit to be programmed, the user must submit an encryption table. the 87c51gb has a 3-level program lock system and a 64-byte encryption array. since this is an eprom device, all locations are user programma- ble. see table 3. encryption array within the programmable array are 64 bytes of en- cryption array that are initially unprogrammed (all 1's). every time that a byte is addressed during a verify, 5 address lines are used to select a byte of the encryption array. this byte is then exclusive- nor'ed (xnor) with the code byte, creating an en- cryption verify byte. the algorithm, with the array in the unprogrammed state (all 1's), will return the code in its original, unmodified form. for program- ming the encryption array, refer to table 2. when using the encryption array feature, one impor- tant factor needs to be considered. if a code byte has the value 0ffh, verification of the byte will pro- duce the encryption byte value. if a large block ( l 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. for this reason it is strongly recommended that all unused code bytes be programmed with some value other than 0ffh, and not all of them the same value. this practice will ensure the maximum possible program protection. program lock bits the 87c51gb has 3 programmable lock bits that when programmed according to table 3 will provide different levels of protection for the on-chip code and data . the 83c51gb has 1 program lock bit. see line 2 of table 3. reading the signature bytes the 8XC51GB has 3 signature bytes in locations 30h, 31h, and 60h. to read these bytes follow the procedure for verify, but activate the control lines provided in table 2 for read signature byte. location contents 87c51gb 83c51gb 30h 89h 89h 31h 58h 58h 60h ebh ebh/6bh table 3. program lock bits and the features * program lock bits protection type lb1 lb2 lb3 1 u u u no program lock features enabled. (code verify will still be encrypted by the encryption array if programmed). 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, also external execution is disabled. * any other combination of lock bits is not defined. 19
8XC51GB otp programming and verification characteristics (t a e 21 cto27 c; v cc e 5v g 20%; v ss e 0v) symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 75 ma 1/tclcl oscillator frequency 4 6 mhz tavgl address setup to prog low 48tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after prog 48tclcl tehsh (enable) high to v pp 48tclcl tshgl v pp setup to prog low 10 m s tghsl v pp hold after prog 10 m s tglgh prog width 90 110 m s tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable 0 48tclcl tghgl prog high to prog low 10 m s programming and verification waveforms 272337 22 * 25 pulses for encryption table and lock bits. 20
8XC51GB a/d glossary of terms absolute errore the maximum difference between corresponding actual and ideal code transitions. ab- solute error accounts for all deviations of an actual converter from an ideal converter. actual characteristice the characteristic of an ac- tual converter. the characteristic of a given convert- er may vary over temperature, supply voltage, and frequency conditions. an actual characteristic rarely has ideal first and last transition locations or ideal code widths. it may even vary over multiple conver- sions under the same conditions. break-before-makee the property of a multiplexer which guarantees that a previously selected channel will be deselected before a new channel is selected (e.g., the converter will not short inputs together). channel-to-channel matchinge the difference be- tween corresponding code transitions of actual char- acteristics taken from different channels under the same temperature, voltage and frequency condi- tions. characteristice a graph of input voltage versus the resultant output code for an a/d converter. it de- scribes the transfer function of the a/d converter. codee the digital value output by the converter. code centere the voltage corresponding to the midpoint between two adjacent code transitions. code transitione the point at which the converter changes from an output code of q, to a code of q a 1. the input voltage corresponding to a code tran- sition is defined to be that voltage which is equally likely to produce either of two adjacent codes. code widthe the voltage corresponding to the dif- ference between two adjacent code transitions. crosstalke see ``off-isolation''. dc input leakagee leakage current to ground from an analog input pin. differential non-linearitye the difference be- tween the ideal and actual code widths of the termi- nal based characteristic. feedthroughe attenuation of a voltage applied on the selected channel of the a/d converter after the sample window closes. full scale errore the difference between the ex- pected and actual input voltage corresponding to the full scale code transition. ideal characteristice a characteristic with its first code transition at v in e 0.5 lsb, its last code tran- sition at v in e (v ref b 1.5 lsb) and all code widths equal to one lsb. input resistancee the effective series resistance from the analog input pin to the sample capacitor. lsbeleast significant bite the voltage corre- sponding to the full scale voltage divided by 2 n , where n is the number of bits of resolution of the converter. for an 8-bit converter with a reference voltage of 5.12v, one lsb is 20 mv. note that this is different than digital lsbs since an uncertainty of two lsbs, when referring to an a/d converter, equals 40 mv. (this has been confused with an un- certainty of two digital bits, which would mean four counts, or 80 mv). monotonice the property of successive approxi- mation converters which guarantees that increasing input voltages produce adjacent codes of increasing value, and that decreasing input voltages produce adjacent codes of decreasing value. no missed codese for each and every output code, there exists a unique input voltage range which produces that code only. non-linearitye the maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal char- acteristic. off-isolatione attenuation of a voltage applied on a deselected channel of the a/d converter. (also re- ferred to as crosstalk.) repeatabilitye the difference between corre- sponding code transitions from different actual char- acteristics taken from the same converter on the same channel at the same temperature, voltage and frequency conditions. resolutione the number of input voltage levels that the converter can unambiguously distinguish between. also defines the number of useful bits of information which the converter can return. sample delaye the delay from receiving the start conversion signal to when the sample window opens. sample delay uncertaintye the variation in the sample delay. sample timee the time that the sample window is open. sample time uncertaintye the variation in the sample time. 21
8XC51GB sample windowe begins when the sample capaci- tor is attached to a selected channel and ends when the sample capacitor is disconnected from the se- lected channel. successive approximatione an a/d conversion method which uses a binary search to arrive at the best digital representation of an analog input. temperature coefficientse change in the stated variable per degree centrigrade temperature change. temperature coefficients are added to the typical values of a specification to see the effect of temperature drift. terminal based characteristice an actual charac- teristic which has been rotated and translated to re- move zero offset and full scale error. v cc rejectione attenuation of noise on the v cc line to the a/d converter. zero offsete the difference between the expected and actual input voltage corresponding to the first code transition. data sheet revision summary the following differences exist between this data- sheet and the previous version (270869-003): 1. merged 87c51gb express (270889-001). 2. new order number 272337-001. the following differences exist between the 270869- 003 data sheet and the previous version (270869- 002): 1. changed data sheet status from ``advance infor- mation'' to ``preliminary'' and updated associated notices. 2. added 83c51gb throughout. 3. added package and process information. 4. clarified g 2 lsb accuracy for channels 0 and 1 in a/d converter section. 5. added ``rom and eprom lock system'' section and added 83c51gb to ``program lock bits'' section. 6. modified signature bytes table. the following differences exist between the 270869-002 data sheet and the previous version (270869-001): 1. changed data sheet status from ``product pre- view'' to ``advance information'' and updated as- sociated notices. 2. asynchronous port reset was added to reset pin description. 3. ale disable paragraph was added to ale pin de- scription. 4. c 1 ,c 2 guidelines clarified in figure 4. 5. operating conditions heading was added. 6. maximum i ol per i/o pin was added to absolute maximum ratings. 7. vt a ,vt b ,v hys ,v ol2 , and v tl removed. 8. v ol value for ale included with v ol1 . 9. v il1 and v il2 added. 10. rrst minimum changed from 40k to 50k. rrst maximum changed from 225k to 300k. 11. i pd maximum changed from 200 m ato50 m a. 12. i dl maximum changed from 15 ma to 18 ma. 13. typical values for i pd ,i dl ,i cc , and i ref re- moved. 14. note 3 (page 9) was reworded. 15. sep ac timings added. 16. a/d absolute error for channels 0 and 1 changed to g 2 lsb. 17. t cy clarified. 18. encryption array paragraph was added. 19. corrected pin numbers on figure 11 to reflect plcc package. 22

▲Up To Search▲

Price & Availability of 8XC51GB

	To Download 8XC51GB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .